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1 HD66420 (ram-provided 160 channel 4-level grey scale driver for dot matrix graphics lcd) description the HD66420 drives and controls a dot matrix graphic lcd(liquid crystal display) using a bit-mapped method. it provides a highly flexible display through its on-chip display ram, in which each two bits of data can be used to turn on or off one dot on lcd panel with four-level grey scale. a single HD66420 can display a maximum of 160x80 dots using its powerful display control functions. it can display only eight lines out of eighty lines. this function realize low power consumption because high voltage for driving lcd is not needed. an mpu can access HD66420 at any time, because the mpu operations are asynchronous with the HD66420? system clock and display operation. its low-voltage operation at 2.2 to 5.5v and standby function provides low power dissipation, making the HD66420 suitable for small portable device applications. features built-in bit-mapped display ram: 25.6kbits (160 80 2 bits) grey scale display: pwm four-level grey scale can be selected from 32 levels grey scale memory management: packed pixel partial display: eight-lines data can be displayed in any place an 80-system mpu interface power supply voltage for operation : 2.2v to 5.5v power supply voltage for lcd : 13 v max. selectable multiplex duty ratio: 1/8, 1/32, 1/64, 1/80 built-in oscillator: external resister low power consumption: ? 55 m a typ. 80 m a max. during display ? 0.1 m a typ. 5 m a max. during standby circuits for generating lcd driving voltage : contrast control, operational amplifier, and resistive dividers internal resistive divider: programmable bias rate 32-level programmable contrast control
HD66420 2 wide range of instructions reversible display, display on/off, vertical display scroll, blink, reversible address, read-modify-write mode package: tcp ordering information type no. package HD66420ta0 tcp
HD66420 3 pin arrangement note: this figure is not drawn to a scale com80 com79 com78 com41 seg160 seg159 seg158 com40 seg3 seg2 seg1 com39 com3 com2 com1 i/o,power supply pins lcd drive signal output pins gnd1 vlcd1 vcc1 v5o v4o v3o v2o v1o gref irefm irefp vlcd2 vlcd3 vcc2 gnd2 gnd3 vcc3 osc1 osc2 osc co dcon cl1 flm m m/s res cs rs wr rd vcc4 gnd4 db0 db1 db2 db3 db4 db5 db6 db7 vcc5 gnd5 vcc6 vlcd4 gnd6
HD66420 4 pin description pin name number of pins i/o connected to description v cc 1?, gnd1? 12 power supply v cc : +2.2v to +5.5v, gnd: 0v vlcd1? 4 power supply power supply to lcd driving circuit v1o, v2o, v3o, v4o, v5o 5 v1 to v5 of HD66420 several levels of power to the lcd driving outputs. master HD66420 outputs these levels to the slave HD66420. osc 1 i oscillator resister or must be connected to external resister when using r-c oscillation. when using an external clock, it must be osc1, osc2 2 i/o external clock input to the osc terminal. co 1 o osc of slave HD66420 clock output dcon 1 o external dc/dc convertor controls on/off switch of external dc/dc convertor cl1 1 i/o cl1 of HD66420 line clock flm 1 i/o flm of HD66420 frame signal m 1 i/o m of HD66420 converts lcd driving outputs to ac m/s 1 i v cc or gnd specifies master/slave mode. res 1 i reset the lsi internally when drive low. cs 1 i mpu select the lsi, specifically internal registers (index and data registers) when driven low. rs 1 i mpu select one of the internal registers; select the index register when driven low and data registers when driven low. wr 1 i mpu inputs write strobe; allows a write access when driven low. rd 1 i mpu inputs read strobe; allows a read access when driven low. db7 to db0 8 i/o mpu 8-bits three-state bidirectional data bus; transfer data between the HD66420 and mpu through this bus. seg1 to seg160 160 o lcd output column drive signals com1 to com80 80 o lcd output row drive signals irefp 1 v cc power supply for internal operation amplifier irefm 1 external resistor bias current for internal operational amplifier gref 1 gnd power supply for internal operation amplifier
HD66420 5 resister list index reg.bits data bits cs rs 4 3 2 1 0 register name r/w 7 6 5 4 3 2 1 0 1 0 0 ir index register w ir4 ir3 ir2 ir1 ir0 0 1 0 0 0 0 0 r0 control register 1 w rmw disp stby pwr amp rev holt adc 0 1 0 0 0 0 1 r1 control register 2 w bis1 bis0 wls gray dty1 dty0 inc blk 0 1 0 0 0 1 0 r2 x address register w xa5 xa4 xa3 xa2 xa1 xa0 0 1 0 0 0 1 1 r3 y address register w ya6 ya5 ya4 ya3 ya2 ya1 ya0 0 1 0 0 1 0 0 r4 display ram access register r/w d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 1 0 1 r5 display start line register w st6 st5 st4 st3 st2 st1 st0 0 1 0 0 1 1 0 r6 blink start line register w bsl6 bsl5 bsl4 bsl3 bsl2 bsl1 bsl0 0 1 0 0 1 1 1 r7 blink end line register w bel6 bel5 bel4 bel3 bel2 bel1 bel0 0 1 0 1 0 0 0 r8 blink register 1 w bk0 bk1 bk2 bk3 bk4 bk5 bk6 bk7 0 1 0 1 0 0 1 r9 blink register 2 w bk8 bk9 bk10 bk11 bk12 bk13 bk14 bk15 0 1 0 1 0 1 0 r10 blink register 3 w bk16 bk17 bk8 bk9 0 1 0 1 0 1 1 r11 partial display block register w pb3 pb2 pb1 pb0 0 1 0 1 1 0 0 r12 gray scale palette 1 (0, 0) w gp14 gp13 gp12 gp11 gp10 0 1 0 1 1 0 1 r13 gray scale palette 2 (0, 1) w gp24 gp23 gp22 gp21 gp20 0 1 0 1 1 1 0 r14 gray scale palette 3 (1, 0) w gp34 gp33 gp32 gp31 gp30 0 1 0 1 1 1 1 r15 gray scale palette 4 (1, 1) w gp44 gp43 gp42 gp41 gp40 0 1 1 0 0 0 0 r16 contrast control register w cm1 cm0 cc4 cc3 cc2 cc1 cc0 0 1 1 0 0 0 1 r17 reserved 0 1 1 0 0 1 0 r18 reserved 0 1 1 0 0 1 1 r19 reserved 0 1 1 0 1 0 0 r20 reserved 0 1 1 0 1 0 1 r21 reserved 0 1 1 0 1 1 0 r22 reserved 0 1 1 0 1 1 1 r23 reserved 0 1 1 1 0 0 0 r24 reserved 0 1 1 1 0 0 1 r25 reserved 0 1 1 1 0 1 0 r26 reserved 0 1 1 1 0 1 1 r27 reserved 0 1 1 1 1 0 0 r28 reserved 0 1 1 1 1 0 1 r29 reserved 0 1 1 1 1 1 0 r30 reserved 0 1 1 1 1 1 1 r31 reserved
HD66420 6 rmw rmw = 1: read-modify-write mode; address is incremented only after write access rmw = 0: address is incremented after both write and read access disp disp = 1: display on disp = 0: display off stby stby = 1:internal operation and power circuit halt; display off stby = 0: normal operation pwr pwr = 1: output ?igh?from dcon pwr = 0: output ?ow?from dcon amp amp = 1: op amp enable amp = 0: op amp disable re v rev = 1: reverse display rev = 0: normal display holt holt = 1: internal operation stops, oscillator works holt = 0: internal operation starts adc adc = 1: data in x address h? is output from seg160 adc = 0: data in x address h? is output from seg1 bis1, 0 bis1, 0 = (1,1): 1/6 lcd drive levels bias ratio bis1, 0 = (1,0): 1/7 lcd drive levels bias ratio bis1, 0 = (0,1): 1/8 lcd drive levels bias ratio bis1, 0 = (0,0): 1/9 lcd drive levels bias ratio wls wls = 1: 6-bit data is valid wls = 0: 8-bit data is valid gray gray = 1: grayscale palette is available(gray scales can be selected from 32-levels) gray = 0: grayscale palette is not available(4-gray scales fixed)
HD66420 7 dty1, 0 dty1, 0 = (1,1): 1/8 display duty cycle - partial display dty1, 0 = (1,0): 1/32 display duty cycle dty1, 0 = (0,1): 1/64 display duty cycle dty1, 0 = (0,0): 1/80 display duty cycle inc inc = 1: x address is incremented for each access inc = 0: y address is incremented for each access blk blk = 1: blink function is used blk = 0: blink function is not used
HD66420 8 block diagram rd wr cs rs db7 -db0 osc res osc2 v3o v2o v5o v4o vlcd flm m cl1 co dcon v1o osc1 m/s column driver y decoder x decoder row counter 320 x 80bit display memory level shifter data latch2 data latch1 com1 com40 seg1 seg160com41 com80 x address counter start line register attribute comparator blink end line register blink start line register control register mpu interface display line counter row driver oscillator lcd driver power supply, contrast control y address counter data buffer timing generator grey scale selector grey scale palette 320 160 level shifter grey scale pattern generator contrast control register decoder 320 320 row driver level shifter i/o control blink registers mpx
HD66420 9 system description the HD66420 can display a maximum of 160 80 dots (ten 16x16-dot characters 5 lines) four-level gray scale or four colour lcd panel. four levels of gray scale can be selected from 32-levels, so the appropriate 4-level gray scale can be displayed. the HD66420 can reduce power dissipation without affecting display because data is retained in the display ram even during standby modes. an lcd system can be configured simply by attaching external power supply, capacitors and resistors (figure 1) since the HD66420 incorporates power circuits. com1 to com40 HD66420 lcd panel mpu 8 seg1 to seg160 cs rs rd wr db7 to db0 com41 to com80 dc/dc convertor figure 1 system block diagram
HD66420 10 mpu interface the HD66420 can interface directly to an mpu through an 8-bit data bus or through an i/o port (figure 2). the mpu can access the HD66420 internal registers independently of internal clock timing. the index register can be directly accessed but the other registers (data registers) cannot. before accessing a data register, its register number must be written to the index register. once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. an example of a register access sequence is shown in figure 3. c0 c1 c2 c3 a0 - a7 cs rs rd wr db0 - db7 h8/325 HD66420 8 a) interface through bus a15 - a0 a0 rd wr d0 - d7 cs rs rd wr db0 - db7 z80 HD66420 8 b) interface through i/o port decoder figure 2 8-bit mpu interface examples
HD66420 11 rd wr db7 to db0 write index register rs cs write data register write index register read data register read data register data data data data data data write data register figure 3 8-bit data transfer sequence
HD66420 12 lcd driver configuration row and column outputs: the HD66420 outputs row signals from both sides. in any case, each output? function is fixed; com1 to com80 output row signals and seg1 to seg160 output column signals. dot-matrix display 40-channel row output 160-channel column output 40-channel row output row outputs from both sides of lcd 160 80 HD66420 com41 to com80 com1 to com40 seg1 to seg160 figure 4 common outputs from both sides
HD66420 13 column address inversion according to lcd driver layout: the hd6420 can always display data in address h? on the top left of an lcd panel regardless of where it is positioned with respect to the panel. this is because the HD66420 can invert the positional relationship between display ram addresses and lcd driver output pins by inverting ram addresses. specifically, the HD66420 outputs data in address h? from seg1 when the adc bit in control register 1 is 0, and from seg160 otherwise. here, the scan direction of row output is also inverted according to the situation as shown in figure 6. note that addresses and scan direction are inverted when data is written to the display ram, and thus changing the adc bit after data has been written has no effect. therefore. hardware control bits such as adc must be set immediately after reset is canceled, and must not be set while data is being displayed. com1 com40 lcd panel com80 com41 b) adc = 1 seg1 seg2 seg3 seg158 seg159 seg160 seg157 seg156 seg155 seg154 seg153 com80 com41 com1 com40 a) adc = 0 h? seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg158 seg159 seg160 lcd panel h? HD66420 HD66420 h? h? figure 5 lcd driver layout and ram addresses : 1/80 duty cycle table 1 scanning direction and ram address dty1 dty0 adc common segment 0 0 0 com1 ? com40, com80 ? com41 h?0 ? seg1 1 com41 ? com80, com40 ? com1 h?0 ? seg160 1 0 com1 ? com32, com80 ? com49 h?0 ? seg1 1 com49 ? com80, com32 ? com1 h?0 ? seg160 1 0 0 com1 ? com16, com80 ? com65 h?0 ? seg1 1 com65 ? com80, com16 ? com1 h?0 ? seg160 1 0 8 com depend on r11 h?0 ? seg1 1 8 com depend on r11 h?0 ? seg160
HD66420 14 multi-lsi operation using multiple HD66420s provides the means for extending the number of display dots. note the following items when using the multi-lsi operation. (1) the master lsi and the slave lsi must be determined; the m/s pin of the master lsi must be set high and the m/s pin of the slave lsi must be set low. (2) the master lsi supplies the flm, m, cl1 and clock signals to the slave lsi via the corresponding pins, which synchronizes the slave lsi with the master lsi. (3) all control bits of slave lsi must be set with the same data with that of the master lsi. (4) all lsis must be set to lcd off in order to turn off the display. (5) the standby function of slave lsi must be started up first, and that of the master lsi must be terminated first. (6) the power supply circuit of slave lsi stop working, so v1 to v5 levels are supplied from the master lsi. if the internal power supply circuit can not drive two lsis, use an external power supply circuit. figure 6 shows the configuration using two HD66420s and table 2 lists the differences between master and slave modes. dot-matrix display 40-channel row output 160-channel column output 40-channel row output 320 x 80 HD66420 (master) 160-channel column output HD66420 (slave) cl1 flm m cl1 flm m osc co osc osc1 co osc1 open v1o to v5o v1o to v5o figure 6 configuration using two HD66420s
HD66420 15 table 2 comparison between master and slave modes item master mode slave mode pin m/s must be set high must be set low osc oscillation is active oscillation is active co output high-z flm, m, cl1 output signals input signals registers r0, r2 to r15 valid valid r1: bis1, 0 valid invalid r1: other valid valid r16 valid invalid power supply circuit valid invalid
HD66420 16 display ram configuration and display the HD66420 incorporates a bit-mapped display ram. it has 320 bits in the x direction and 80 bits in the y direction. the 320 bits are divided into forty 8-bit groups. as shown in figure 6, data written by the mpu is stored horizontally with the msb at the far left and the lsb at the far right. the consecutive two bits control one pixel of lcd, this means that one 8-bits data contains data which controls four pixels. the adc bit of control register 1 can control the positional relationship between x addresses of the ram and lcd driver output (figure 7). specifically. the data in address h? is output from seg1 when the adc bit in control register 1 is 0, and from seg160 otherwise. here, data in each 8-bit group is also inverted. because of this function, the data in x address h? can be always displayed on the top left of an lcd panel with the msb at the far left regardless of the lsi is positioned with respect to the panel. in this case, db7, db5, db3 and db1 are more significant bit in consecutive two bits. seg1 seg2 seg3 seg4 11 100 100 00 011 011 y0 y1 d b 7 d b 1 lcd panel display ram seg157 seg158 deg159 seg160 11 100 100 00 011 011 y0 y1 d b 7 d b 0 lcd panel display ram d b 6 d b 4 d b 5 d b 2 d b 3 d b 1 d b 6 d b 5 d b 4 d b 3 d b 2 d b 0 (a) adc = 0 (b) adc = 1 seg160 seg1 figure 7 display ram data and display
HD66420 17 h?0 h?1 h? h? h?7 x addresses seg1 seg160 lcd drive signal output (a) adc = 0 (b) adc = 1 h?e h?f h?0 h?1 h? h?6 h?7 seg1 seg160 h?e h?f y address msb msb lcd drive signal output y address x addresses figure 8 display ram configuration
HD66420 18 word length the HD66420 can handle either 8- or 6-bits as a word. in the display memory, one x address is assigned to each word of 8- or 6-bits long in x direction. when the 6-bits mode is selected, only data on db5 to db0 are used and data on db7 and db6 are discarded. this word length is only applied to data to internal ram. the word length of internal register is always 8-bits h?0 h?1 h? h? h?7 x addresses seg1 seg160 lcd drive signal output (a) address assignment when one word is 8 bits long h?e h?f h?0 h?1 h?5 h? h? seg1 seg160 h?e h?f y address msb msb lcd drive signal output y address x addresses h?4 (b) address assignment when one word is 6 bits long 8 bits 6 bits figure 9 display ram addresses
HD66420 19 11 100 1 00 011 0 y0 y1 d b 1 display ram 100 011 d b 1 d b 0 d b 4 d b 0 d b 3 d b 2 d b 5 d b 4 (a) wls= 1, adc = 0 h?5? bit7,6, and 3 to 0 are disable . (b) wls= 1, adc = 1 h?? bit7 to 2 are disable. 11 1001 00 0110 y0 y1 d b 5 display ram 100 011 d b 5 d b 4 d b 0 d b 4 d b 3 d b 2 d b 1 d b 0 h? h?5 h?5 h? figure 10 display ram bits map
HD66420 20 configuration of display data bit packed pixel method for grey scale display and super reflective colour display, multiple bits are needed for one pixel. in the HD66420, two bits are assigned to one pixel, enabling a four-level grey scale display and four colour display. one address, eight bits, specifies four pixels, and pixel bits 0 and 1 for gray scale are managed as consecutive bits in one byte. when grey scale display data is manipulated in bit units, one memory access is sufficient, which enables smooth high-speed data rewriting. the bit data to input to pin db7, db5, db3 and db1 become msb and the bit data to input via pin db6, db4, db2 and db0 are lsb. 000 11011 765 43210 bit frc control circuit grey scale/colour palette physical memory lcd display state 000 01010 765 43210 4 pixels/address address: n address: n + 1 figure 11 packed pixel method
HD66420 21 gray scale/colour palette the HD66420 uses pwm, pulse width modulation, technique for gray scale display. a period of one line is divided into thirty-one or four and HD66420 outputs turn-on levels for one period and turn-off levels for rest of these period. this technique changes gray scale on monochrome display and colour on super reflective colour panel. the characteristics of these panel vary with different panel. to allow for this, the HD66420 designed to generate 32-levels gray scale levels and provides palette registers that assign desired levels to certain of the four colours, gray = 0, or generate dedicated 4-level grayscale , gray = 1. using the palette registers to select any 4 out of 32 levels of applied voltages enables an optimal grayscale/colour display. because of this grayscale technique using 32-levels gray scale needs higher clock rate. if 32-levels gray scale is not needed, lower clock rate can be used. table 3 shows default value of palette registers and table 4 and 5 show relationship between value of a palette register and grayscale level. table 3 default value of palette registers db7, 5, 3, 1 db6, 4, 2, 0 register name default value 0 0 grayscale palette 1 0 0 0 0 0 1 grayscale palette 2 0 1 0 1 1 1 0 grayscale palette 3 1 0 1 1 1 1 grayscale palette 4 1 1 1 1 1
HD66420 22 table 4 value of a palette register and grayscale levels (gray= 0) value grayscale level 0 0 0 0 0 0 defaust r12 1 1/31 1 0 2/31 1 3/31 1 0 0 4/31 1 5/31 1 0 6/31 1 7/31 1 0 0 0 8/31 1 9/31 1 0 10/31 1 11/31 defaust r13 1 0 0 12/31 1 13/31 1 0 14/31 1 15/31 1 0 0 0 0 16/31 1 17/31 1 0 18/31 1 19/31 1 0 0 20/31 1 21/31 1 0 22/31 1 23/31 defaust r14 1 0 0 0 24/31 1 25/31 1 0 26/31 1 27/31 1 0 0 28/31 1 29/31 1 0 30/31 1 1 defaust r15
HD66420 23 table 5 grayscale levels (gray= 1) db7, 5, 3, 1 db6, 4, 2, 0 grayscale level 00 0 1 1/3 1 0 2/3 11 access to internal registers and display ram access to internal registers by the mpu: the internal registers include the index register and data registers. the index register can be accessed by driving both the cs and rs signals low. to access a data register, first write its register number id to the index register with rs set to 0, and then access the data register with rs set to 1 . once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. some data registers contain unused bits; they should be set to 0. note that all data registers except the display memory access register can only be written to. access to display ram by the mpu: to access the display ram, first write the ram address desired to the x address register (r2) and the y address register (r3). then read/write the display memory access register (r4). memory access by the mpu is independent of memory read by the HD66420 and is also asynchronous with the HD66420? clock, thus enabling an interface independent of HD66420? internal operations. however, when reading. data is temporarily latched into a h66420? buffer and then output next time, a read is performed in a subsequent cycle. this means that a dummy read is necessary after setting x and y addresses. the memory read sequence is shown in figure 12. x and y addresses are automatically incremented after each memory access according to the inc bit value in control register 2; therefore, it is not necessary to update the addresses for each access. figure 13 shows two cases of incrementing display ram address. when the inc bit is 0, the y address will be incremented up to h?f with the x address unchanged. however, actual memory is valid only within h?0_ to h?f; accessing an invalid address is ignored. when the inc bit is 1 , the x address will be incremented up to h?7 or h?5 according to wls bit with the y address unchanged. after address h?7 or h?5, the x address will be returned to h?0; accessing more than forty bytes causes rewriting to the same address.
HD66420 24 [n] [m] data[n,m] data[n,m+1] undetermined h?2 h?3 h?4 wr input data output data dummy read [n,*] [n,m] [n,m+1] [n,m+2] [*,*] address rs rd x address y address figure 12 display ram read sequence
HD66420 25 display ram reading by lcd controller: data is read by the HD66420 to be displayed asynchronously with accesses by the mpu. however, because simultaneous access could damage data in the display ram, the HD66420 internally arbitrates access timing; access by the mpu usually has priority and so access by the HD66420 is placed between accesses by the mpu. accordingly, an appropriate time must be secured (see the given electrical characteristics between two accesses by the mpu). a) inc = 0 h? h? h?7 h?0 h?1 h?f h?8 h?5 wls= 0 wls= 1 b) inc = 1 h? h? h?7 h?0 h?1 h?2 h?f h?8 h?5 wls= 0 wls= 1 wls= 0 wls= 1 h?f valid area invalid area valid area (wls= 1) invalid area figure 13 display address increment
HD66420 26 read-modify-write: x- or y-address is incremented after reading form or writing data to the display ram at normal mode. however, x- or y-address is not incremented after reading data from the display ram at read-modify-write mode. the data which is read from the display ram may be modified and written to the same address without re-setting the address. data is temporarily latched into a HD66420? buffer and then output next time a read is performed in a subsequent cycle. this means that the dummy read is necessary after every cycle. this sequence is shown in figure 14. set x-address set y-address dummy read read data write data finish modifying no yes address incremented start end figure 14 the flow chart for read-modify-write
HD66420 27 vertical scroll function the HD66420 can vertically scroll a display by varying the top raster to be displayed. which is specified by the display start raster register. figure 15 and 16 show vertical scroll examples. as shown, when the top raster to be displayed is set to l, data in y address h?0_ is displayed on the 80th raster. to display another frame on the 80th raster, therefore, data in y address h?0_ must be modified after setting the top raster. when display duty is less than 80, for example 1/64, data of address h?0 is displayed after address h?f.
HD66420 28 h?0 h?1 h?2 h?3 h?4 h?5 h?6 h?7 h?8 h?9 h?a h?c h?d h?e h?f y-address top raster to be displayed = 0 top raster to be displayed = 2 y-address h?0 h?1 h?e h?f h?b h?c h?2 h?3 h?4 h?5 h?6 h?7 h?8 h?9 h?a y-address top raster to be displayed = 1 h?b h?1 h?2 h?3 h?4 h?5 h?6 h?7 h?8 h?9 h?a h?0 h?d h?e h?f figure 15 vertical scroll : 1/80duty cycle
HD66420 29 y-address y-address top raster to be displayed = 0 top raster to be displayed = 1 top raster to be displayed = 2 y-address h?0 h?1 h?2 h?3 h?4 h?5 h?6 h?7 h?8 h?9 h?a h?c h?d h?e h?f h?b h?1 h?2 h?3 h?4 h?5 h?6 h?7 h?8 h?9 h?a h?0 h?d h?e h?f h?c h?2 h?3 h?4 h?5 h?6 h?7 h?8 h?9 h?a h?e h?f h?1 h?b h?0 figure 16 vertical scroll : 1/64duty cycle
HD66420 30 partial display function the HD66420 can display only a part of a full display. the bias ratio of this partial display is 1/4 from v cc to gnd, the duty ratio is 1/8 and rest of display is scanned with unselected levels. 8 levels of contrast can be selected wit data bit 2 to 0 of r16. the position of this partial display can be located at any position with using partial display position register. to launch this mode, following processes are needed: (1) supplied voltage to vlcd must be cut off, pwr bit can be used if external voltage supplier is controlled with dcon output (r0) (2) set dty0, 1 bits (r1) (3) set com scanning direction (adc bit) (4) set display position (r11, r5) (5) set contrast level (r16 data-bit 2 to 0) the clock frequency may be 180khz at normal display mode. when a partial display is driven, oscillation frequency will be 18khz, 1/10 of that of normal display mode. this function is useful for lower power dissipation. to change clock frequency, follow the process which is showed in figure 21. warning: vlcd must be cut off when partial display mode is launched. vcc is supplied to lcd driving circuit instead of vlcd. so if vlcd is supplied externally during partial display mode, vcc short-circuit to vlcd. table 6 partial display block r11 adc = 1 adc = 0 h?0 com1 ? com8 com8 ? com1 h?1 com9 ? com16 com16 ? com9 h?2 com17 ? com24 com24 ? com17 h?3 com25 ? com32 com32 ? com25 h?4 com33 ? com40 com40 ? com33 h?5 com80 ? com73 com73 ? com80 h?6 com72 ? com65 com65 ? com72 h?7 com64 ? com57 com57 ? com64 h?8 com56 ? com49 com49 ? com56 h?9 com48 ? com41 com41 ? com48
HD66420 31 display ram y address h?0 lcd panel com1 com33 com40 com80 com41 h?f r5 start line r5+7 r11 = h?4 abcd abcd figure 17 partial display
HD66420 32 blink function the HD66420 can blink a specified area on the dot-matrix display. blinking is achieved by repeatedly turning on and off the specified area at a frequency of one sixty-fourth the frame frequency. for example, when the frame frequency is 80 hz. the area is turned on and off every 0.8 seconds. the area to be blinked can be designated by specifying vertical and horizontal positions of the area. the vertical position or the rasters to be blinked, are specified by the blink start raster register (r6) and blink end raster register (r7). the horizontal position, or the dots to be blinked in the specified rasters, are specified by the blink registers r8, r9 and r10 in an 8-dot group; each data bit in the blink registers controls its corresponding 8-dots group. the relationship between the registers and blink area is shown in figure 18. setting the blk bit to 1 in control register 2 after setting the above registers starts blinking the designated area. note that since the area to be blinked is designated absolutely with respect to the display ram, it will move along with a scrolling display (figure 19). 0 000 00 111 110 000 1 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 blink start line (r6) blink end line (r7) blink registers r8 r9 blink area seg1 lcd seg9 seg17 seg25 seg33 seg41 seg49 seg57 seg65 seg73 seg81 seg89 seg97 seg105 seg113 seg121 seg129 seg137 seg145 seg153 00 0 1 seg160 d b 3 d b 2 d b 1 d b 0 r10 figure 18 blink area designation by blink control registers
HD66420 33 display start raster = 0 blink start raster = 0 blink end raster = h? display start raster = h? blink start raster = h? blink end raster = h? figure 19 scrolling blink area
HD66420 34 power down modes the HD66420 has a standby function providing low power-dissipation, which is initiated by internal register settings. during standby mode, all the HD66420 functions are inactive and data in the display ram and internal registers except the disp bit are retained. however, only control registers can be accessed during standby mode. HD66420 has an another power down mode: partial display. in this mode only a part of display is active. however, this duty ratio is 1/8 so the external power supply for lcd drive will be inactive. the oscillator does not halt, thus dissipating more power than standby mode. table 7 lists the lcd driver output pin status during standby mode. figure 20 shows the procedure for initiating and canceling a standby mode and figure 21 shows the procedure for changing oscillator. note that these procedure must be strictly followed to protect data in the display ram. table 7 output pin status during power down modes signal name stby status com1?om80 1 output vlcd (display off) 0 output common signals (vlcd?nd) seg1?eg160 1 output vlcd (display off) 0 output segment signals (vlcd?nd) set stby bit to 1 (control register 1) clear stby and pwr bits to 0 (control register 1) oscillation halts external power supply off oscillator starts internal operation starts display starts standby mode initiation cancellation wait for oscillation and external power supply to stabilize set disp bit to 1 (control register 1) figure 20 procedure for initiation and canceling a standby mode
HD66420 35 set holt bit to 1 (control register 1) set dty or gray bit to 1 (control register 2) internal operation stops oscillator 2 starts working wait for oscillation to stabilize clear holt bit to 0 (control register 1) internal operation starts figure 21 procedure for changing oscillator
HD66420 36 power on/off procedure figure 22 shows the procedure for turning the power supply on and off. this procedure must be strictly followed to prevent incorrect display because the HD66420 incorporates a power supply circuit. boosting starts power on turn on power (power-on reset) set pwr bit to 1 (control register 1) write data to registers and ram as required set disp bit to 1 (control register 1) set cnf, adc, dty1, dty0, inc bits according to the operating mode (control register1 and 2) turn off power clear disp bit to 0 (control register 1) power off boosting halts clear pwr bit to 0 (control register 1) figure 22 procedure for turning power supply on/off
HD66420 37 oscillator the HD66420 incorporates two sets of r-c oscillator for two display modes: osc-osc1 oscillator is used for 32-levels gray scale display mode and osc-osc2 oscillator for 4-levels gray scale display mode. if the internal oscillator is not used, an appropriate clock signal must be externally input through the osc pin. in this case, the osc1 and osc2 pins must be left unconnected. oscillation resister must be placed near lsi, because if capacitance exists between osc and osc1 oscillator may not work properly. figure 23 shows oscillator connections. changing oscillator two oscillators are alternated automatically depending on modes. the resistor between osc and osc1 is used during 32-levels grayscale mode and the resistor between osc and osc2 is used during 4-levels grayscale mode. an external clock must be input from osc terminal at any modes. clock and frame frequency the HD66420 generates the frame frequency by dividing the input clock. clock frequency is determined with following equation: f osc = n * (duty ratio) * (frame frequency) n: 31 for 32-level gray scale display mode 3 for 4-level gray scale display mode the frame frequency is usually 70 to 90 hz; when the frame frequency is 70 hz, for example, the input clock frequency will be 180 khz for 32-level gray scale display mode, and 18khz for 4-level gray scale. osc osc2 clock (open) osc osc1 HD66420 HD66420 a) external clock b) dual oscillator rf1 osc1 (open) osc2 osc osc1 HD66420 c)single oscillator rf osc2 (open) rf2 figure 23 oscillator connections
HD66420 38 power supply circuits HD66420 has following circuits for power supply circuit: operational amplifiers, resistive dividers, bias control circuit and contrast control circuit. lcd driving voltage, vlcd, must be generated externally. lcd drive voltage power supply levels: to drive the lcd, a 6-level power supply is necessary. these levels are generated internally or supplied from outside. when an internal voltage levels generator is chosen, external capacitors are needed to stabilize these levels. as the HD66420 incorporates operational amplifiers to these levels, this circuit gives better quality of display with less power consumption. this divided ratio is programmable. bias current of internal operational amplifier is determined with a resister which is inserted between irefm and gnd. this resister value is between 1m w and 5m w . larger resister value make less power consumption at internal operational amplifier. however, too large value loose operational margin of amplifiers. keep following relationship among voltage levels; v cc 3 irefmp > irefm 3 gnd vlcd > v cc > gref 3 gnd vlcd 3 v1o 3 v2o 3 v3o 3 v4o 3 v5o 3 gref vlcd? cc 3 1.0v irefp?refm 3 1.0v v cc ?ref 3 1.0v contrast control: internal contrast control circuit can change the output voltage level of vlcd by setting data to contrast control register, r16. vlcd adjustable range are showed below; 1/6 bias 0.75 * (vlcd-gnd) vlcd 0.99 * (vlcd-gnd) 1/9 bias 0.82 * (vlcd-gnd) vlcd 0.993 * (vlcd-gnd)
HD66420 39 0 v5o v4o v3o v2o v1o vlcd example.1 lcd bias level 1/80 duty display (1/9 bias, vlcd = 12v, gnd = 0v) voltage [v] 0 1 2 3 4 5 6 7 8 9 10 11 12 07 0f contrast (r16) 17 1f (maximum) 0 v5o v4o v3o v2o v1o v cc example.2 lcd bias level partial display (1/4 bias, vcc = 5v, gnd = 0v) voltage [v] 0 1 2 3 4 5 4 contrast (r16) 7 (maximum) partial display 0.82 * (v cc -gnd) v cc 0.997 (v cc -gnd) partial display function uses 1/4 bias ratio from v cc to gnd. eight levels of contrast can be selected with data bit 2 to 0 of r16. lcd drive levels bias ratio: lcd driving levels bias ratio can be selected from 1/6, 1/7, 1/8 or 1/9. power supply: the HD66420 needs the external power supply for lcd driving circuit. if this power circuit has on/off control, the HD66420 controls the external power supply circuit by setting pwr bit. external power supply circuit: when the internal operational amplifier cannot fully drive the lcd panel used, v1o to v5o voltages can be supplied from external power supply circuit. here, the amp bit must be set to 1 to turn off the internal power supply circuit.
HD66420 40 - + - + - + - + v2o v3o v4o v5o iv1 iv2 iv3 iv4 gref r1 r1 r3 r1 r1 vlcd r2 contrast control circuit bias control v1o HD66420 dcon external voltage booster on/off vout - + iv5 r4 irefp irefm gnd vcc vlcd operational amplifier off resistive divider for partial display mode r r r r r1 = r r2 = 0.0625r to 2r r3 = 2r to 5r r4 = 1m to 5m c1 = 1 f to 3 f resister for bias current of operational amplifier c1 c1 c1 c1 c1 figure 24 power supply circuit
HD66420 41 reset the low res signal initializes the HD66420, clearing all the bits in the internal registers. during reset. the internal registers cannot be accessed. note that if the reset conditions specified in the electric characteristics section are not satisfied, the HD66420 will not be correctly initialized. in this case, the internal registers of the HD66420 must be initialized by software. initial setting of internal registers: all the internal register bits are cleared to 0. details are listed below. ? normal operation ? oscillator is active; osc-osc1 is used ? display is off ? y address of display ram is incremented ? 1/80 duty cycle ? x and y addresses are 0 ? data in address h? is output from the segl pin ? blink function is inactive ? operational amplifier is disabled initial setting of pins: bus interface pins during reset, the bus interface pins do not accept signals to access internal registers; data is undefined when read. lcd driver output pins during reset. all the lcd driver output pins (seg1 to segl61, com1 to com80) output vcc-level voltage, regardless of data value in the display ram, turning off the lcd. here, the output voltage is not alternated. note that the same voltage (vlcd) is applied to both column and row output pins to prevent liquid crystals from degrading. internal registers the HD66420 has one index register and 17 data registers, all of which can be accessed asynchronously with the internal clock. all the registers except the display memory access register are write-only. accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to. index register (ir): the index register (figure 25) selects one of 17 data registers. the index register itself is selected when both the cs and rs signals are low. data bits 7 to 5 are unused; they should be set to 0 when written to.
HD66420 42 control register 1 (r0): control register 1 (figure 26) controls general operations of the HD66420. each bit has its own function as described below. rmw bit rmw = l: read-modify-write mode address is incremented only after write access rmw = 0: address is incremented after both write and read accesses disp bit disp = 1: display on disp = 0: display off (all lcd driver output pins output vlcd level) stby bit stby = l: internal operation and oscillation halt; display off stby = 0: normal operation pwr bit pwr = l: output high level from dcon terminal pwr = 0: output low level from dcon terminal this bit controls the external power supply for lcd driving outputs. amp bit amp = 1: op amp enable amp = 0: op amp disable rev bit rev = 1: reverse display rev = 0: normal display holt bit holt = l : internal operation stops holt = 0: internal operation starts adc bit adc = l: data in x address h? is output from seg160; row signals depend on duty. adc = 0: data in x address h? is output from seg1; row signals are scanned from com1. data bit set value 765 432 10 register number figure 25 index register (ir)
HD66420 43 data bit set value 7654321 0 rmw disp stby pwr amp rev holt adc figure 26 control register 1 (r0) control register 2 (r1): control register 2 (figure 27) controls general operations of the HD66420. each bit has its own function as described below. bis1, bis0 bits bis1, 0 = (1, 1): 1/6 lcd drive levels bias ratio bis1, 0 = (1, 0): 1/7 lcd drive levels bias ratio bis1, 0 = (0, 1): 1/8 lcd drive levels bias ratio bis1, 0 = (0, 0): 1/9 lcd drive levels bias ratio wls bit wls = l: a word length is 6-bits wls = 0: a word length is 8-bits gray bit gray = l : 4-levels of gray scale are fixed gray = 0: 4-levels of gray scale are selected from 32-levels dty1,dty0 bits dty1, 0 = (1, 1): 1/8 display duty cycle; partial display mode dty1, 0 = (1, 0): 1/32 display duty cycle dty1, 0 = (0, 1): 1/64 display duty cycle dty1, 0 = (0, 0): 1/80 display duty cycle inc bit i nc = l: x address is incremented for each access inc = 0: y address is incremented for each access blk bit blk = 1: blink function is used blk = 0: blink function is not used the blink counter is reset when the blk bit is set to 0. it starts counting and at the same time initiates blinking when the blk bit is set to l. x address register (r2): the x address register (figure 28) designates the x address of the display ram to be accessed by the mpu. the set value must range from h?0 to h?7 in the case of 8-bit a word or range from h?0 to h?5 in the case of 6-bit a word; setting a greater value is ignored. the set address is automatically incremented each time the display ram is accessed; it is not necessary to update the address each time. data bits 7 and 6 are unused; they should be set to 0 when written to.
HD66420 44 y address register (r3): the y address register (figure 29) designates the y address of the display ram to be accessed by the mpu. the set value must range from h?0 to h?0; setting a greater value is ignored. the set address is automatically incremented each time the display ram is accessed; it is not necessary to update the address each time. data bit 7 is unused; it should be set to 0 when written to. data bit set value 7654321 0 wls gray dty1 dty0 inc blk bis0 bis1 figure 27 control register 2 (r1) data bit set value 7654321 0 xa5 xa4 xa3 xa2 xa1 xa0 figure 28 x address register (r2) data bit set value 76 543 21 0 ya6 ya5 ya4 ya3 ya2 ya1 ya0 figure 29 y address register (r3) display memory access register (r4): the display memory access register (figure 30) is used to access the display ram. if this register is write-accessed, data is directly written to the display ram. if this register is read-accessed, data is first latched to this register from the display ram and sent out to the data bus on the next read; therefore, a dummy read access is necessary after setting the display ram address. display start raster register (r5): the display start raster register (figure 31) designates the raster to be displayed at the top of the lcd panel. varying the set value scrolls the display vertically. the set value must be one less than the actual top raster and less than the duty ratio. if the value is set outside these ranges, data may not be displayed correctly. data bits 7 is unused; they should be set to 0 when written to. blink start raster register (r6): the blink start raster register (figure 32) designates the top raster in the area to be blinked. the set value must be one less than the actual top raster and less than the duty ratio. if the value is set outside these ranges, operations may not be correct. data bits 7 is unused; they should be set to 0 when written to. blink end raster register (r7): the blink end register (figure 33) designates the bottom raster in the area to be blinked. the area to be blinked is designated by the blink registers, blink start raster register, and blink end raster register. the set value must be one less than the actual bottom raster and less than the duty ratio.
HD66420 45 it must also be greater than the value set in the blink start raster register. if an inappropriate value is set, operations may not be correct. data bits 7 is unused; they should be set to 0 when written to. data bit set value 7 6 54321 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 30 display memory access register (r4) data bit set value 7654321 0 st5 st4 st3 st2 st1 st0 st6 figure 31 display start raster register (r5) data bit set value 7654321 0 bsl5 bsl4 bsl3 bsl2 bsl1 bsl0 bsl6 figure 32 blink start raster register (r6) data bit set value 76543210 bel5 bel4 bel3 bel2 bel1 bel0 bel6 figure 33 blink end raster register (r7) blink registers (r8 to r10): the blink bit registers (figure 34) designate the 8-bit groups to be blinked. setting a bit to 1 blinks the corresponding 8-bit group. any number of groups can be blinked; setting all the bits to 1 will blink the entire lcd panel. these bits are valid only when the blk bit of control register 2 is 1. r10? data bits 7 to 4 are unused; they should be set to 0 when written to. partial display block register (r11): the partial display block register (figure 35) designates the block of partial display. data bits 7 and 4 are unused; they should be set to 0 when written to. gray scale palette registers (r12 to r15): the gray scale palette registers (figure 36) designate the grayscale level or colour. use these registers to enable an optimal grayscale or colour display. if gray bit is 1, these registers are inactive. data bits 7 to 5 are unused; they should be set to 0 when written to.
HD66420 46 data bit set value 7654321 0 bk0 bk1 bk2 bk3 bk4 bk5 bk6 bk7 set value bk8 bk9 bk10 bk11 bk12 bk13 bk14 bk15 set value bk16 bk17 bk18 bk19 r8 r9 r10 figure 34 blink registers (r8, r9, r10) data bit set value 765 432 10 pb3 pb2 pb1 pb0 set value h?0 h?1 h?2 h?3 h?4 row no. com1 to com8 com9 to com16 com17 to com24 com25 to com32 com33 to com40 set value h?5 h?6 h?7 h?8 h?9 row no. com80 to com73 com72 to com65 com64 to com57 com56 to com49 com48 to com41 (adc= ?? if ??, reverse direction) figure 35 partial display start raster register (r11) data bit set value 7654321 0 gp14 gp13 gp12 gp11 gp10 set value gp24 gp23 gp22 gp21 gp20 set value gp34 gp33 gp32 gp31 gp30 set value gp44 gp43 gp42 gp41 gp40 r12 r13 r14 r15 figure 36 grayscale palette registers (r12 to r15) contrast control and lcd alternative drive cycle register (r16): the contrast control register (figure 37) designates the contrast level of lcd display. these bits change the voltage which is supplied to lcd drivers. the lcd alternative drive cycle register designates the number of lines that lcd drive outputs are alternated. data bits 7 is unused; they should be set to 0 when written to.
HD66420 47 table 8 grayscale levels gp14 gp24 gp34 gp44 gp13 gp23 gp33 gp43 gp12 gp22 gp32 gp42 gp11 gp21 gp31 gp41 gp10 gp20 gp30 gp40 gray scale level gp14 gp24 gp34 gp44 gp13 gp23 gp33 gp43 gp12 gp22 gp32 gp42 gp11 gp21 gp31 gp41 gp10 gp20 gp30 gp40 gray scale level 000000 10000 16/31 1 1/31 1 17/31 1 0 2/31 1 0 18/31 1 3/31 1 19/31 1 0 0 4/31 1 0 0 20/31 1 5/31 1 21/31 1 0 6/31 1 0 22/31 1 7/31 1 23/31 1000 8/31 1000 24/31 1 9/31 1 25/31 1 0 10/31 1 0 26/31 1 11/31 1 27/31 1 0 0 12/31 1 0 0 28/31 1 13/31 1 29/31 1 0 14/31 1 0 30/31 1 15/31 1 1 table 9 lcd alternative drive cycle cm1 cm0 alternative cycle 0 0 frame 0 0 7 lines 0 0 11 lines 0 0 13 lines data bit set value 76543210 cc3 cc2 cc1 cc0 cc4 cm0 cm1 figure 37 contrast control register (r16)
HD66420 48 absolute maximum ratings item symbol ratings unit notes power supply voltage logic circuit v cc ?.3 to +7.0 v 1 lcd drive circuit vlcd ?.3 to +15.0 v input voltage 1 vt1 ?.3 to v cc + 0.3 v 1, 2 input voltage 2 vt2 0.3 to vlcd + 0.3 v 1, 3 operation temperature t opr ?0 to +85 c storage temperature t stg ?5 to +110 c notes: 1. measured relative to gnd 2. applies to pins m/ s , osc, osc1, osc2, db7 to db0, rd , wr , cs , rs, res , cl1, m, flm 3. applies to pins v1o, v2o, v3o, v4o and v5o 4. if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics to prevent malfunction or unreliability.
HD66420 49 electrical characteristics dc characteristics (v cc = 2.2 to 5.5v, gnd = 0v, vlcd = 6 to 13v, ta = ?0 to +85 c) *10 item symbol terminals min typ max unit test condition notes i/o leakage current iiol ? 1 m a vin = v cc to gnd 1 v-pins leakage current ivl ?0 10 m a vin = gnd to vlcd 2 driver on resistance ron seg1 to seg160 com1 to com80 20 k w i on = 100 m a vlcd = 6 v 3 input high voltage vih1 0.8 v cc ? cc v1 input low voltage vil1 0 0.2 v cc v1 output high voltage voh db7 to db0 0.8 v cc ? cc vi oh = ?0 m a4 output low voltage vol db7 to db0 0 0.2 v cc vi ol = 50 m a4 current consumption during display idisp v cc ?580 m av cc =3.0 v rf = 24 k w 5, 6 ?540 m a 5, 7 current consumption during standby istb v cc ?5 m a 5, 8 current consumption lcd drive part ilcd vlcd 30 50 m a 5, 9 note: 1. applies to pins: m/s, cs , rs, wr , rd , res , osc, db7 to db0, cl1, m and flm 2. applies to pins: v0o, v1o, v2o, v3o, v4o and v5o 3. indicates the resistance between one pin from seg1 to seg160and another pin from v1o to v5o v1o and v2o should be near vlcd level, and v3o to v5o should be near gnd level. all voltage must be within d v. d v is the range within which ron is stable. v1 to v4 levels should keep following condition:vlcd 3 v1o 3 v2o 3 v3o 3 v4o 3 v5o 3 gnd 4. applies to pins: db7-db0, co, cl1, m and flm 5. input and output current are excluded. when a cmos input is floating, excess current flows from power supply to the input circuit. to avoid this, vih and vil must be held to vcc and gnd levels, respectively. the current which flows at resistive divider and lcd are excluded. where the unmolded side of lsi is exposed to light , excess current flows. use under sealed condition. 6. specified under following conditions: internal oscillator is used; rf = 240k w 32-levels gray scale mode; gray = 0 v cc = 3.0v checker board is displayed no access fro cpu 7. specified under following conditions: internal oscillator is used; rf = 240k w
HD66420 50 4-levels gray scale mode; gray = 1 v cc = 3.0v checker board is displayed no access fro cpu 8. measured during stand-by mode. v cc = 3.0v 9. specified under following conditions: internal power supply circuit is used. resister value is 5m w which is connected between irefm and gnd v cc = 3.0v, vlcd = 12v, irefp = v cc , gref = gnd 10. specified at +75 c for die products. input terminal input enable i/o terminal pins: db7 to db0, flm, m, cl1 output enable data output terminal pins: co data pins: cs, rs, wr, rd, res, m/s figure 38 terminal configuration
HD66420 51 ac characteristics (v cc = 2.2v to 5.5v, gnd = 0v, ta = ?0 to +85 c) * clock characteristics item symbol min typ max unit notes oscillation frequency f osc 130 180 230 khz rf = 240 k w , v cc = 3.0 v external clock frequency f cp 50 400 khz external clock duty cycle duty 45 50 55 % external clock fall time t r 0.2 m s external clock rise time t f 0.2 m s reset timing item symbol min typ max unit notes res low-level width t res 1ms note: specified at +75 c for die products. mpu interface item symbol min typ max unit notes rd low-level width t wrdl 250 ns v cc = 2.2 v to 3.0 v 190 khz v cc = 3.0 v to 5.5 v rd high-level width t wrdh 450 ns wr low-level width t wwrl 250 ns v cc = 2.2 v to 3.0 v 190 ns v cc = 3.0 v to 5.5 v wr high-level width t wwrh 450 ns address setup time t as 10 ns address hold time t ah 10 ns data delay time t ddr 180 ns v cc = 2.2 v to 3.0 v 150 ns v cc = 3.0 v to 5.5 v data output hold time t dhr 10 ns data setup time t dsw 150 ns v cc = 2.2 v to 3.0 v 100 m sv cc = 3.0 v to 5.5 v data hold time t dhw 10 ns
HD66420 52 t wrdl t wrdh t wwrl t wwrh t as t ah t ddr t dhr t dsw t dhw t as t ah rd wr rs,cs db7- db0 figure 39 mpu interface

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